0 – July. 1. Qualification Package. AT89C51ED2. FLASH 8-bit C51 Microcontroller. 64 Kbytes FLASH, 2 Kbytes EEPROM. AT89C51RD2 / AT89C51ED2. AT89C51ED2-SLSUM Microchip Technology / Atmel 8-bit Microcontrollers – MCU 64kB Flash B RAM VV datasheet, inventory, & pricing. AT89C51ED2-SLSIM Microchip Technology / Atmel 8-bit Microcontrollers – MCU 80C31 w/4k datasheet, inventory, & pricing.

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Set to enable a high level detection on Port line 7. An internal counter will count clock periods before the reset is de-asserted. Added Flash write programming time specification. Hardware conditions or regular boot process. The WDT is by default disabled from exiting reset. VIH min changed from 0. In this mode, program execution halts. Do not try to set this bit.

Do not set this bit 6 – Reserved The value read from this bit is indeterminate. When the pin is pulled low, it is driven strongly and able to sink a fairly large current. The programming voltage is internally generated from the standard VCC pin. Set to configure the SPI as a Master. Figure gives a logical view of the above statements.

Page 8 Table To communicate with slave A only, the master must send an address where bit 0 is clear e. Page 44 Figure The command “Program Software Security Bit” can only write a higher priority level. Page 38 Table It is driven by the Master for eight clock cycles which allows to exchange one Byte on the serial lines.



Your manual failed to upload Its advantages include reduced software overhead and improved accuracy. RST input has a pull-down resistor allowing power-on reset by simply connecting an external capacitor to V CC as shown in Figure Can also be set by software. This page, called “Extra Flash Memory”, is not in the internal Flash program memory addressing space.

PCA interrupt enable bit Cleared to disable. Once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL clock input. Page 54 Table This signal must stay low for any message for a Slave. MODF is set to warn that there may be a multimaster conflict for system control.

AT89C51ED2 – Microcontrollers and Processors – Microcontrollers and Processors

Page 34 Table The four segments are: Generate an enabled external Keyboard interrupt same behavior as external interrupt. Page 12 Table Set to enable keyboard interrupt. These API are executed by the bootloader.

Don’t see a manual you are looking for? Security level 2 and 3 should only be programmed after Flash verification.

Must be cleared by software. Tell us about it. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set e. There are three levels of security: Output pulse for latching at89c51e2 low byte of the address during an access to external memory.


Set by hardware when VCC rises from 0 to its nominal voltage. Cleared by hardware when programming is done. Oscillator To optimize the power consumption and execution time needed for a specific task, an internal prescaler feature has been implemented between the oscillator and the CPU and peripherals. Pins are not guaranteed to sink current greater than the listed test conditions.

Setting TR2 allows TL2 to increment by the selected input. Page 42 Table Set to enable all interrupts. When the communication is initialized, the protocol depends on the record type requested by the host.

The Kbytes Flash memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. Only one Master SPI device can initiate transmissions. Power-Down mode stops the oscillator, freezes all clock at known states.